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DATA SHEET
MOS INTEGRATED CIRCUIT
MC-45V8AB642KS
8M-WORD BY 64-BIT VirtualChannel DYNAMIC RAM MODULE (SO DIMM)
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Description
The MC-45V8AB642KS is a 8,388,608 words by 64 bits VirtualChannel dynamic RAM module (small outline DIMM)
on which 4 pieces of 128M VirtualChannel DRAM : PD45V128161 are assembled. This module provides high density and large quantities of memory in a small space without utilizing the surface-
mounting technology on the printed circuit board. Decoupling capacitors are mounted on power supply line for noise reduction.
Features
* 8,388,608 words by 64 bits organization
* Clock frequency and access time from CLK
Part number Read Clock
MC-45V8AB642KS-A75
* Fully Standard Synchronous Dynamic RAM, with all signals referenced to a positive clock edge * Dual internal banks controlled by BA0 (Bank Select) * Programmable wrap sequence (interleave) * Programmable burst length (4) * Read latency (2) * Prefetch read latency (4) * Auto precharge and without auto precharge * Auto refresh and self refresh * Single 3.3 V 0.3 V power supply * Interface: LVTTL * Refresh cycle: 4K cycles/64 ms * Unbuffered type * Serial PD
* 144-pin small outline dual in-line memory module (Pin pitch = 0.8 mm)
Document No. E0028N11 (Ver. 1.1) (Previous No. M15239EJ1V0DS00) Date Published April 2001 CP (K) Printed in Japan
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latency frequency MHz (MAX.) 2 133
Access time from CLK ns (MAX.)
Maximum supply current mA Operating Prefetch Restore Channel Refresh Auto Self
The information in this document is subject to change without notice. Before using this document, please confirm that this is the latest version.
Not all devices/types available in every country. Please check with local Elpida Memory, Inc. for availability and additional information.
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5.4 600
read / write (Burst) 300 920 8
This Product became EOL in January, 2003.
Elpida Memory, Inc. is a joint venture DRAM company of NEC Corporation and Hitachi, Ltd.
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Ordering Information
Clock Part number frequency MHz (MAX.) MC-45V8AB642KS-A75 133 Read latency 2 Prefetch read latency 4 144-pin Small Outline DIMM (Socket Type) Edge connector : Gold plated 25.4 mm height 4 pieces of PD45V128161G5 (10.16 mm (400) TSOP (II)) Package Mounted devices
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MC-45V8AB642KS
Pin Configuration
144-pin Small Outline Dual In-line Memory Module Socket Type (Edge connector: Gold plated)
/xxx indicates active low signal.
2 4 6 8 10 12 14 16 18 20 22 24 26 28 30 32 34 36 38 40 42 44 46 48 50 52 54 56 58 60 Vss DQ 32 DQ 33 DQ 34 DQ 35 Vcc DQ 36 DQ 37 DQ 38 DQ 39 Vss DQMB4 DQMB5 Vcc A3 A4 A5 Vss DQ 40 DQ 41 DQ 42 DQ 43 Vcc DQ 44 DQ 45 DQ 46 DQ 47 Vss NC NC Vss DQ 0 DQ 1 DQ 2 DQ 3 VCC DQ 4 DQ 5 DQ 6 DQ 7 Vss DQMB0 DQMB1 VCC A0 A1 A2 Vss DQ 8 DQ 9 DQ 10 DQ 11 VCC DQ 12 DQ 13 DQ 14 DQ 15 Vss NC NC 1 3 5 7 9 11 13 15 17 19 21 23 25 27 29 31 33 35 37 39 41 43 45 47 49 51 53 55 57 59
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62 64 66 68 70 72 74 76 78 80 82 84 86 88 90 92 94 96 98 100 102 104 106 108 110 112 114 116 118 120 122 124 126 128 130 132 134 136 138 140 142 144
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CLK0 CKE0 Vcc Vcc /RAS /CAS /WE NC /CS0 NC NC NC NC CLK1 Vss Vss NC NC NC NC VCC Vcc DQ 16 DQ 48 DQ 17 DQ 49 DQ 18 DQ 50 DQ 19 DQ 51 Vss Vss DQ 20 DQ 52 DQ 21 DQ 53 DQ 22 DQ 54 DQ 23 DQ 55 Vcc Vcc A6 A7 A8 BA0 (A13) Vss Vss A9 A12 A10 A11 Vcc Vcc DQMB2 DQMB6 DQMB3 DQMB7 Vss Vss DQ 24 DQ 56 DQ 25 DQ 57 DQ 26 DQ 58 DQ 27 DQ 59 VCC Vcc DQ 28 DQ 60 DQ 29 DQ 61 DQ 30 DQ 62 DQ 31 DQ 63 Vss Vss SDA SCL VCC Vcc
61 63 65 67 69 71 73 75 77 79 81 83 85 87 89 91 93 95 97 99 101 103 105 107 109 111 113 115 117 119 121 123 125 127 129 131 133 135 137 139 141 143
A0 - A12 BA0 (A13)
: Address Inputs : VirtualChannel DRAM Bank Select : Data Inputs/Outputs : Clock Input : Clock Enable Input : Chip Select Input : Row Address Strobe : Column Address Strobe : Write Enable : DQ Mask Enable : Serial Data I/O for PD : Power Supply : Ground
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CKE0 /CS0 /RAS /WE /CAS SDA SCL VCC VSS NC
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[Row: A0 - A12, Column: A0 - A6]
DQ0 - DQ63 CLK0, CLK1
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DQMB0 - DQMB7
: Clock Input for PD
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MC-45V8AB642KS
Block Diagram
/WE /CS0 DQMB0 DQ 0 DQ 1 DQ 2 DQ 3 DQ 4 DQ 5 DQ 6 LDQM DQ 0 DQ 1 DQ 2 DQ 3 DQ 4 DQ 5 DQ 6 DQ 7 UDQM DQ 15 DQ 14 DQ 13 DQ 12 DQ 11 DQ 10 DQ 9 DQ 8 D0
/CS /WE
DQMB4 DQ 32 DQ 33 DQ 34 DQ 35 DQ 36 DQ 37 DQ 38 DQ 39 DQMB5 DQ 40 DQ 41 DQ 42 DQ 43 DQ 44 DQ 45 DQ 46 DQ 47
LDQM DQ 0 DQ 1 DQ 2 DQ 3 DQ 4 DQ 5 DQ 6 DQ 7 UDQM DQ 15 DQ 14 DQ 13 DQ 12 DQ 11 DQ 10 DQ 9 DQ 8
/CS
/WE
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DQ 7 DQMB1 DQ 8 DQ 9 DQ 10 DQ 11 DQ 12 DQ 13 DQ 14 DQ 15 DQMB2 DQ 16 DQ 17 DQ 18 DQ 19 DQ 20 DQ 21 DQ 22 DQ 23 DQMB3 DQ 24 DQ 25 DQ 26 DQ 27 DQ 28 DQ 29 DQ 30 DQ 31 SCL A0 - A12 BA0
D2
Remark
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LDQM
/CS
/WE
DQ 7 DQ 6 DQ 5 DQ 4 DQ 3 DQ 2 DQ 1 DQ 0
DQMB6 DQ 48 DQ 49 DQ 50 DQ 51 DQ 52 DQ 53 DQ 54
LDQM DQ 7 DQ 6 DQ 5 DQ 4 DQ 3 DQ 2 DQ 1 DQ 0 UDQM DQ 8 DQ 9 DQ 10 DQ 11 DQ 12 DQ 13 DQ 14 DQ 15
/CS
/WE
D0 - D3: PD45V128161 (4M words x 16 bits x 2 banks)
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D1 DQ 55 UDQM DQ 8 DQ 9 DQMB7 DQ 56 DQ 57 DQ 58 DQ 59 DQ 60 DQ 61 DQ 62 DQ 10 DQ 11 DQ 12 DQ 13 DQ 14 DQ 15 DQ 63 SERIAL PD VCC SDA VSS A0 A1 A2 CLK0 /RAS A0 - A12 : D0 - D3 A13 : D0 - D3 /CAS CKE0
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D0 - D3 D0 - D3 C 10 CLK : D0 - D3 CLK1 /RAS : D0 - D3 /CAS : D0 - D3 CKE : D0 - D3
10 pF
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MC-45V8AB642KS
Electrical Specifications
* All voltages are referenced to VSS (GND). * After power up, wait more than 100 s and then, execute power on sequence and auto refresh before proper device operation is achieved. Absolute Maximum Ratings
Parameter Voltage on power supply pin relative to GND Voltage on input pin relative to GND Short circuit output current Power dissipation Symbol VCC VT IO PD TA Tstg Condition Rating -0.5 to +4.6 -0.5 to +4.6 50 4 0 to 70 -55 to +125 Unit V V mA W C C
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Storage temperature Parameter Supply voltage High level input voltage Low level input voltage Parameter Input capacitance
Operating ambient temperature
Caution Exposing the device to stress above those listed in Absolute Maximum Ratings could cause permanent damage. The device is not meant to be operated under conditions outside the limits described in the operational section of this specification. Exposure to Absolute Maximum Rating conditions for extended periods may affect device reliability.
Recommended Operating Conditions
Symbol VCC VIH VIL TA Condition MIN. 3.0 2.0 -0.3 0 TYP. 3.3 MAX. 3.6 VCC + 0.3 +0.8 70 Unit V V V C
Operating ambient temperature
Capacitance (TA = 25 C, f = 1 MHz)
Symbol CI1 CI2 CI3 CI4 CI5 Data input/output capacitance CI/O
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Test condition A0 - A12, BA0 (A13), /RAS, /CAS, /WE CLK0 CKE0 /CS0 DQMB0 - DQMB7 DQ0 - DQ63
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MIN. 15 TYP. 23 15 15 5 5
MAX. 30
Unit pF
37 26
26 10
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12 pF
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MC-45V8AB642KS
DC Characteristics (Recommended Operating Conditions Unless Otherwise Noted)
Parameter Operating current (Prefetch mode at one bank active) Operating current (Restore mode at one bank active) Precharge standby current in power down mode ICC2P CKE VIL (MAX.), tCK = 15 ns 4.8 4.8 80 40 24 24 120 mA mA mA mA ICC1R Symbol Test condition ICC1P tRC tRC (MIN.) Prefetch is executed one time during tRC. tRC tRC (MIN.) -A75 600 mA 1 Grade -A75 MIN. MAX. 600 Unit Notes mA 1
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Precharge standby current in non power down mode Active standby current in power down mode Active standby current in non power down mode Operating current (Burst mode) Auto Refresh current Self refresh current Input leakage current Output leakage current High level output voltage Low level output voltage
ICC2PS CKE VIL (MAX.), tCK = ICC2N CKE VIH (MIN.), tCK = 15 ns, /CS VIH (MIN.), Input signals are changed one time during 30 ns. ICC2NS CKE VIH (MIN.), tCK = , Input signals are stable. ICC3P CKE VIL (MAX.), tCK = 15 ns
ICC3PS CKE VIL (MAX.), tCK = ICC3N CKE VIH (MIN.), tCK = 15 ns, /CS VIH (MIN.), Input signals are changed one time during 30 ns. ICC3NS CKE VIH (MIN.), tCK = , Input signals are stable. ICC4 tCK tCK (MIN.), IO = 0 mA -A75
80 300 mA 2
Notes 1. ICC1 depends on output loading and cycle rates. Specified values are obtained with the output open. In addition to this, ICC1 is measured on condition that addresses are changed only one time during tCK (MIN.). 2. ICC4 depends on output loading and cycle rates. Specified values are obtained with the output open. In addition to this, ICC4 is measured on condition that addresses are changed only one time during tCK (MIN.). 3. ICC5 is measured on condition that addresses are changed only one time during tCK (MIN.).
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ICC5 ICC6 II (L) IO (L) VOH VOL
Background : precharge standby tRCF tRCF
(MIN.)
-A75 -A75 -4 -1.5 2.4
920 8 +4 +1.5
mA mA
3
CKE 0.2 V VI = 0 to 3.6 V, All other pins not under test = 0 V DOUT is disabled, VO = 0 to 3.6 V
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IO = - 4.0 mA IO = + 4.0 mA
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AC Characteristics (Recommended Operating Conditions unless otherwise noted)
Test Conditions * AC measurements assume tT = 1 ns. * Reference level for measuring timing of input signals is 1.4 V. Transition times are measured between VIH and VIL. * If tT is longer than 1 ns, reference level for measuring timing of input signals is VIH (MIN.) and VIL (MAX.). * An access time is measured at 1.4 V.
tCK tCH tCL tCK tCL
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CLK CKE Command Address DQM (Input) Data (Input) Data (Output)
tCKS
tCKH
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tS tH Valid tAC tLZ Hi-Z
tDS
tDH
tDS
tDH
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Valid tAC tOH Valid
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Valid
tHZ Hi-Z
Valid
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AC characteristics
Parameter Symbol MIN. Clock cycle time Access time from CLK CLK high level width CLK low level width Data-out hold time tCK2 tAC2 tCH tCL tOH tLZ tHZ2 tDS tDH tS tH tCKS tCKH tCKSP tT tREF tRSC 7.5 - 2.5 2.5 2.7 0 2.5 1.5 0.8 1.5 0.8 1.5 0.8 1.5 0.5 - 2 -A75 MAX. - 5.4 - - - - 5.4 - - - - - - - 30 64 - ns ns ns ns ns ns ns ns ns ns ns ns ns ns ns ms CLK 1 1 Unit Note
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Data-out low-impedance time Data-in setup time Data-in hold time CKE setup time CKE hold time Transition time Mode register set cycle time
Data-out high-impedance time
Address, Command, DQM setup time Address, Command, DQM hold time
CKE setup time (Power down exit)
Refresh time (4,096 refresh cycle)
Note 1. Output load.
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Output
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AC characteristics (Background to Background operation)
Parameter Symbol MIN. 6DPH %DQN 2SHUDWLRQ ACT to ACT/REF Command period REF to REF/ ACT Command period ACT to PRE Command period PRE to ACT / REF Command period ACT to PFC/PFCA Command delay time ACT to PFR Command delay time (Prefetch Read Operation) PFC to PRE Command delay time PFCA / PFR to ACT/REF Command delay time RST / RSTA to ACT(R)
Note1
-A 75 MAX.
Unit Notes
tRC tRCF tRAS tRP tAPD tAPRD tPPL tPAL tRAD
67.5 67.5 52.5 20 15 15 22.5 45 7.5
- - 120,000 - - - - - 30
ns ns ns ns ns ns ns ns ns 2
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ACT(R)
Note1
Command delay time
6DPH 2WKHU %DQN 2SHUDWLRQ
PFC to PFC / PFCA Command delay time
ACT to ACT/ACT(R) or ACT(R) to ACT Command delay time ACT(R) to ACT(R) Command delay time
PFC /PFCA to RST /RSTA Command delay time
Notes 1. ACT (R) command is ACT command after RST command.
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2WKHU %DQN 2SHUDWLRQ
to PFC/PFCA/PFR Command delay time
tRPD tPPD
37.5 22.5
- -
ns ns
tRRD
15
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2. The another background operation and same channel foreground operation are illegal while tRAD period.
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tRRDR tPRD 30 - 22.5 -
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ns ns ns
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AC characteristics (Foreground to Foreground operation)
Parameter Symbol MIN. READ/WRITE to READ/WRITE Command delay time tCCD 7.5 -A 75 MAX. - ns Unit Note
AC characteristics (Background to Foreground operation) (after same channel Prefetch/Restore)
Parameter Symbol MIN. tPCD tRCD 15 30 -A 75 MAX. - - ns ns 1 Unit Note
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10
PFC/PFCA to READ/WRITE Command delay time ACT(R) to READ/WRITE Command delay time
Note 1. ACT (R) command is ACT command after RST command.
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Serial PD
Byte No. 0 Function Described Defines the number of bytes written into serial PD memory 1 Total number of bytes of serial PD memory 2 3 4 5 6 7 8 9 Fundamental memory type Number of row addresses Number of column addresses 08H 0DH 07H 01H 40H 00H 01H 75H 0 0 0 0 0 0 0 0 0 0 0 0 1 0 0 1 0 0 0 0 0 0 0 1 0 0 0 0 0 0 0 1 1 1 0 0 0 0 0 0 0 1 1 0 0 0 0 1 0 0 1 0 0 0 0 0 0 1 1 1 0 0 1 1 VC DRAM 13 rows 7 columns 1 bank 64 bits 0 LVTTL 7.5 ns 08H 0 0 0 0 1 0 0 0 256 bytes Hex 80H Bit 7 1 Bit 6 0 Bit 5 0 Bit 4 0 Bit 3 0 Bit 2 0 Bit 1 0 Bit 0 0
(1/2)
Notes 128 bytes
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Number of banks Data width cycle time 10 access time 11 12 13 14 15 16 17 18 19 20 21 22 23-26 27 28 29 30 tRP (MIN.) tRRD (MIN.) tAPD (MIN.) tRAS (MIN.) Refresh rate / type VC DRAM width
Data width (continued) Voltage interface standard
Read latency (/CAS latency) = 2 -A75
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Read latency (/CAS latency) = 2 -A75 DIMM configuration type Error checking DRAM width Minimum clock delay Burst length supported Number of banks on each VC DRAM Read latency (/CAS latency) supported /CS latency supported /WE latency supported VC DRAM module attributes VC DRAM device attributes : general -A75 -A75 -A75 -A75
54H
0
1
0
1
0
1
0
0
5.4 ns
00H 80H
0 1
0 0
0 0
0 0
0 0 0 0 0 0 0
0 0 0 0 0 1 0
0 0 0 0 0 0 1
0 0 0 0 1 0 0
None Normal x16 None 1 clock 4 2 banks 2 0 0
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10H 0 0 0 1 00H 0 0 0 0 01H 0 0 0 0 04H 02H 0 0 0 0 0 0 0 0 02H 0 0 0 0 01H 0 0 0 0 01H 00H 0 0 0 0 0 0 0 0 0EH 00H 14H 0FH 0FH 34H 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 1 1 0 0 1
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0 0 1 0 0 0 0 1 0 0 0 1 0 0 0 0 1 1 1 0 0 0 0 0 0 1 0 0 1 1 1 1 1 1 1 1 0 1 0 0
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20 ns 15 ns 15 ns 52.5 ns
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(2/2)
Byte No. 31 32 Function Described Module bank density Address and command signal input setup time 33 Address and command signal input hold time 34 35 36 37 38 Data signal input setup time Data signal input hold time -A75 -A75 -A75 -A75 15H 08H 04H 0FH 02H 04H 07H 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 1 0 0 0 0 0 0 0 1 0 1 0 0 0 1 0 1 1 0 1 1 0 0 0 1 1 0 1 1 0 0 1 0 0 1 1.5 ns 0.8 ns 4 clocks 15 ns 2 bits 16 128 bits -A75 08H 0 0 0 0 1 0 0 0 0.8 ns -A75 Hex 10H 15H Bit 7 0 0 Bit 6 0 0 Bit 5 0 0 Bit 4 1 1 Bit 3 0 0 Bit 2 0 1 Bit 1 0 0 Bit 0 0 1 Notes 64M bytes 1.5 ns
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tPCD (MIN.) 39 40 Depth of channels 41-61 62 63 SPD revision 64-71 72 73-90 91-92 93-94 95-98 99-125 Manufacture's P/N Revision code Manufacturing date Mfg specific
Prefetch read latency
Number of segment addresses Number of channels
Timing Charts
Please refer to the PD45V128421, 45V128821, 45V128161 Data sheet (E0025N).
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Checksum for bytes 0 - 62 -A75 Manufacture's JEDEC ID code Manufacturing location Assembly serial number
02H 2AH
0 0
0 0
0 1
0 0
0 1
0 0
1 1
0 0
2.0
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MC-45V8AB642KS
Package Drawing
144-PIN DUAL IN-LINE MODULE (SOCKET TYPE)
A (AREA B) M1 (AREA B) R Y N Q M L
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M2 (AREA A) I F
H C B
A
S
(OPTIONAL HOLES)
U1 T
U2
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E D A1 (AREA A)
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ITEM A A1 B C D D1 E F I D2
MILLIMETERS 67.6 67.60.15 23.2 29.0 4.6 1.50.10 4.0 32.8 3.7 0.8 (T.P.) 3.3 20.0 25.40.15 3.4 22.0 3.8 MAX. R2.0
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H L M M1 M2 N Q R S T U1 U2 V W X Y
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4.00.10 1.8 1.00.1 3.2 MIN. 4.0 MIN. 0.25 MAX. 0.60.05 2.0 MIN. 2.55 MIN.
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Edition / Date Page This edition Previous edition Type of edition Description Location
NEC Corporation (M15239E) 1st edition / Dec.2000 Elpida Memory, Inc. (E0028N) 1st edition / Jan. 2001 - - - - -
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Republished by Elpida Memory, Inc.
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NOTES FOR CMOS DEVICES
1 PRECAUTION AGAINST ESD FOR SEMICONDUCTORS Note: Strong electric field, when exposed to a MOS device, can cause destruction of the gate oxide and ultimately degrade the device operation. Steps must be taken to stop generation of static electricity as much as possible, and quickly dissipate it once, when it has occurred. Environmental control must be adequate. When it is dry, humidifier should be used. It is recommended to avoid using insulators that easily build static electricity. Semiconductor devices must be stored and transported in an anti-static container, static shielding bag or conductive material. All test and measurement tools including work bench and floor should be grounded. The operator should be grounded using wrist strap. Semiconductor devices must not be touched with bare hands. Similar precautions need to be taken for PW boards with semiconductor devices on it. HANDLING OF UNUSED INPUT PINS FOR CMOS
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2 Note: 3 Note:
No connection for CMOS device inputs can be cause of malfunction. If no connection is provided to the input pins, it is possible that an internal input level may be generated due to noise, etc., hence causing malfunction. CMOS devices behave differently than Bipolar or NMOS devices. Input levels of CMOS devices must be fixed high or low by using a pull-up or pull-down circuitry. Each unused pin should be connected to VDD or GND with a resistor, if it is considered to have a possibility of
/
having reset function.
being an output pin. All handling related to the unused pins must be judged device by device and related specifications governing the devices. STATUS BEFORE INITIALIZATION OF MOS DEVICES
Power-on does not necessarily define initial status of MOS device. Production process of MOS does not define the initial operation status of the device. Immediately after the power source is turned ON, the devices with reset function have not yet been initialized. Hence, power-on does not guarantee out-pin levels, I/O settings or contents of registers. Device is not initialized until the reset signal is received. Reset operation must be executed immediately after power-on for devices
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The names of the companies, products, and logos described herein are the trademarks or registered trademarks of each company.
CAUTION FOR HANDLING MEMORY MODULES
When handling or inserting memory modules, be sure not to touch any components on the modules, such as the memory IC, chip capacitors and chip resistors. It is necessary to avoid undue mechanical stress on these components to prevent damaging them. When re-packing memory modules, be sure the modules are NOT touching each other. Modules in contact with other modules may cause excessive mechanical stress, which may damage the modules.
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* The information in this document is current as of April, 2001. The information is subject to change without notice. For actual design-in, refer to the latest publications of Elpida's data sheets or data books, etc., for the most up-to-date specifications of Elpida semiconductor products. Not all products and/or types are available in every country. Please check with an Elpida Memory, Inc. for availability and additional information. * No part of this document may be copied or reproduced in any form or by any means without prior written consent of Elpida. Elpida assumes no responsibility for any errors that may appear in this document. * Elpida does not assume any liability for infringement of patents, copyrights or other intellectual property rights of third parties by or arising from the use of Elpida semiconductor products listed in this document or any other liability arising from the use of such products. No license, express, implied or otherwise, is granted under any patents, copyrights or other intellectual property rights of Elpida or others. * Descriptions of circuits, software and other related information in this document are provided for illustrative purposes in semiconductor product operation and application examples. The incorporation of these circuits, software and information in the design of customer's equipment shall be done under the full responsibility of customer. Elpida assumes no responsibility for any losses incurred by customers or third parties arising from the use of these circuits, software and information. * While Elpida endeavours to enhance the quality, reliability and safety of Elpida semiconductor products, customers agree and acknowledge that the possibility of defects thereof cannot be eliminated entirely. To minimize risks of damage to property or injury (including death) to persons arising from defects in Elpida semiconductor products, customers must incorporate sufficient safety measures in their design, such as redundancy, fire-containment, and anti-failure features. * Elpida semiconductor products are classified into the following three quality grades: "Standard", "Special" and "Specific". The "Specific" quality grade applies only to semiconductor products developed based on a customer-designated "quality assurance program" for a specific application. The recommended applications of a semiconductor product depend on its quality grade, as indicated below. Customers must check the quality grade of each semiconductor product before using it in a particular application. "Standard": Computers, office equipment, communications equipment, test and measurement equipment, audio and visual equipment, home electronic appliances, machine tools, personal electronic equipment and industrial robots "Special": Transportation equipment (automobiles, trains, ships, etc.), traffic control systems, anti-disaster systems, anti-crime systems, safety equipment and medical equipment (not specifically designed for life support) "Specific": Aircraft, aerospace equipment, submersible repeaters, nuclear reactor control systems, life support systems and medical equipment for life support, etc. The quality grade of Elpida semiconductor products is "Standard" unless otherwise expressly specified in Elpida's data sheets or data books, etc. If customers wish to use Elpida semiconductor products in applications not intended by Elpida, they must contact an Elpida Memory, Inc. in advance to determine Elpida's willingness to support a given application. (Note) (1) "Elpida" as used in this statement means Elpida Memory, Inc. and also includes its majority-owned subsidiaries. (2) "Elpida semiconductor products" means any semiconductor product developed or manufactured by or for Elpida (as defined above).
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